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Defines |
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#define | DMA_DST_INC 0 |
| | Incrementing destination address.
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#define | DMA_DST_DEC 0x00200000 |
| | Decrementing destination.
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#define | DMA_DST_FIXED 0x00400000 |
| | Fixed destination.
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#define | DMA_DST_RELOAD 0x00600000 |
| | Increment destination, reset after full run.
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#define | DMA_SRC_INC 0 |
| | Incrementing source address.
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#define | DMA_SRC_DEC 0x00800000 |
| | Decrementing source address.
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#define | DMA_SRC_FIXED 0x01000000 |
| | Fixed source address.
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#define | DMA_REPEAT 0x02000000 |
| | Repeat transfer at next start condition.
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#define | DMA_16 0 |
| | Transfer by halfword.
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#define | DMA_32 0x04000000 |
| | Transfer by word.
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#define | DMA_AT_NOW 0 |
| | Start transfer now.
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#define | DMA_GAMEPAK 0x08000000 |
| | Gamepak DRQ.
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#define | DMA_AT_VBLANK 0x10000000 |
| | Start transfer at VBlank.
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#define | DMA_AT_HBLANK 0x20000000 |
| | Start transfer at HBlank.
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#define | DMA_AT_SPECIAL 0x30000000 |
| | Start copy at 'special' condition. Channel dependent.
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#define | DMA_AT_FIFO 0x30000000 |
| | Start at FIFO empty (DMA0/DMA1).
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#define | DMA_AT_REFRESH 0x30000000 |
| | VRAM special; start at VCount=2 (DMA3).
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#define | DMA_IRQ 0x40000000 |
| | Enable DMA irq.
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#define | DMA_ENABLE 0x80000000 |
| | Enable DMA.
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#define | DMA_COUNT_MASK 0x0000FFFF |
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#define | DMA_COUNT_SHIFT 0 |
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#define | DMA_COUNT(n) ((n)<<DMA_COUNT_SHIFT) |
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#define | DMA_NOW (DMA_ENABLE | DMA_AT_NOW) |
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#define | DMA_16NOW (DMA_NOW | DMA_16) |
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#define | DMA_32NOW (DMA_NOW | DMA_32) |
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#define | DMA_CPY16 (DMA_NOW | DMA_16) |
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#define | DMA_CPY32 (DMA_NOW | DMA_32) |
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#define | DMA_FILL16 (DMA_NOW | DMA_SRC_FIXED | DMA_16) |
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#define | DMA_FILL32 (DMA_NOW | DMA_SRC_FIXED | DMA_32) |
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#define | DMA_HDMA (DMA_ENABLE | DMA_REPEAT | DMA_AT_HBLANK | DMA_DST_RELOAD) |
